1. Field of the Invention
This invention relates to a semiconductor circuit, and more particularly to a power-source wiring of a digital circuit section in a semiconductor integrated circuit that contains the digital circuit section as a first circuit section, and a second circuit section, such as an analog circuit section.
2. Description of the Related Art
FIG. 5 shows a conventional pattern of power source lines for a digital circuit section 40 in a large-scale integrated circuit containing analog circuit sections and digital circuit sections.
Here, numeral 41 indicates a V.sub.cc line; 42 a contact portion of the V.sub.cc line with an n+ region 43 in an n-type semiconductor substrate; 44 a p-channel MOS transistor region formed in the n-type semiconductor substrate; 45 a p-well formed in the n-type semiconductor substrate; 46 an n-channel MOS transistor region formed in the p-well, 47 a V.sub.ss line (the ground potential); and 48 a contact portion of the V.sub.ss line with a p.sup.+ region 49 in the p-well 45.
That is, in the digital circuit section 40, the power source lines 41 and 47 are formed so as to connect to both a circuit element and the substrate (the n-type semiconductor substrate or p-well 45).
In LSI circuits containing both analog and digital circuit sections, electric noise (e.g., noise due to high-speed switching) generated at the digital circuit section 40 often travels along the power source lines 41 and 47, and reaches the substrate via the contact portions 42 and 48 of the lines 41 and 47 with the substrate. It then spreads over the substrate and is absorbed by an analog circuit section (not shown). Such absorption gives an adverse effect on the analog circuit section.
As described above, in conventional semiconductor integrated circuits containing both analog circuit sections and digital circuit sections, the leakage of noises occurring at a digital circuit section into the substrate via the digital circuit power source lines often adversely affects the analog circuit sections.